Ongoing goals of the computer industry include higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits (“IC's”). As new generations of IC products are released, their functionality increases while the number of components needed to fabricate them decreases.
Integrated circuits are constructed from a semiconductor wafer through a process that comprises a number of deposition, masking, diffusion, etching, and implanting steps. Usually, many individual devices are constructed on the same wafer. When the IC's are separated into individual rectangular units, each takes the form of an IC die. In order to interface a die with other circuitry, it is common to mount it on a lead frame or on a multi-chip module substrate that is surrounded by a number of lead fingers. Each die has pads that are then individually connected in a wire bonding or flip chip operation to the lead frame's lead fingers using extremely fine wires or solder balls. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies.
To further condense the packaging of individual devices, packages have been developed in which more than one device can be packaged on a package site of a lead frame strip. Each package site on a lead frame strip is a structure that provides mechanical support for the individual IC dice. It also provides one or more layers of interconnect lines that enable the devices to be connected electrically to surrounding circuitry. Various chip-on-board (“COB”) techniques are used to attach different semiconductor die to a printed circuit board (“PCB”). COB techniques include flip chip attachment, wire bonding, and tape automated bonding (“TAB”).
In some cases, multi-chip devices can be fabricated faster and more cheaply than a corresponding single IC chip that incorporates all the same functions. Current multi-chip modules typically consist of a PCB substrate onto which a set of separate IC chip components is directly attached. Such multi-chip modules have been found to increase circuit density and miniaturization, improve signal propagation speed, reduce overall device size and weight, improve performance, and lower costs, all of which are primary goals of the computer industry.
However, such multi-chip modules can be bulky. The area required to mount a die or module on a circuit board determines the IC package density. One method for reducing the board size of multi-chip modules and thereby increase their effective density is to stack the die or chips vertically within the module or package. In one design, a pair of IC die is mounted on opposite sides of a lead frame paddle. Gold or aluminum wires then connect the wire bonding pads on both the upper die and the lower die with the ends of their associated lead frame lead extensions.
Other representative designs for mounting multiple semiconductor IC chips in a single, multi-chip package include: two chips mounted on two lead frame paddles, one chip mounted over a paddle and one below mounted on a board, and one chip attached on top of a larger chip that is attached below to a paddle. These and other configurations have also been extended to include three or more chips mounted together vertically in a single package.
However, multi-chip modules, whether vertically or horizontally arranged, can also present problems because they usually must be assembled before the component chips and chip connections can be tested. The electrical bond pads on a die are so small, it is difficult to test die before assembly onto a substrate. Thus, when die are mounted and connected individually, the die and connections can be tested individually, and only known-good-die (“KGD”), free of defects, are then assembled into larger circuits. A fabrication process that uses KGD is therefore more reliable and less prone to assembly defects introduced due to bad die. With conventional multi-chip modules, however, the die cannot be individually identified as KGD before final assembly, leading to KGD inefficiencies and assembly process yield problems.
Two of the common die stacking methods are: (a) larger lower die combined with a smaller upper die, and (b) so-called same-size die stacking. With the former, the die can be very close vertically since the electrical bond pads on the perimeter of the lower die extend beyond the edges of the smaller die on top. With same-size die stacking, the upper and lower die are spaced more vertically apart to provide sufficient clearance for the wire bonds to the lower die. As discussed, both these methods have inherent KGD and assembly process yield loss disadvantages since KGD cannot be used for fabricating these configurations.
Another previous design is package level stacking. This concept includes stacking of two or more packages. KGD and assembly process yields are not an issue since each package can be tested prior to assembly, allowing KGD to be used in assembling the stack. But package level stacking can pose other problems. One problem is package-to-package assembly process difficulties caused by irregularities in the flatness or co-planarity of the lower package. Another problem results from the increased stiffness of the overall assembly, which can lead to reduced board level reliability. Still another problem can arise from poor heat dissipation from the upper package.
Thus, despite the improvements of recent developments in semiconductor fabrication and packaging techniques, there is a continuing need for enhanced packaging methods, systems, and designs for increasing semiconductor die density in PCB assemblies. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.